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KM416C256D, KM416V256D
256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
CMOS DRAM
This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
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Fast Page Mode operation 2 CAS Byte/Wrod Read/Write operation CAS-before-RAS refresh capability RAS-only and Hidden refresh capability Self-refresh capability (L-ver only) TTL(5V)/LVTTL(3.3V) compatible inputs and outputs Early Write or output enable controlled write JEDEC Standard pinout Available in 40-pin SOJ 400mil and44(40)-pin TSOP(II) 400mil packages Triple +5V3/410% power supply(5V product) Triple +3.3V3/40.3V power supply(3.3V product)
FEATURES
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Part Identification - KM416C256D/DL (5V, 512K Ref.) - KM416V256D/DL (3.3V, 512K Ref.)
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Active Power Dissipation Unit : mW Speed -5 -6 -7 3.3V(512 Ref.) 325 290 5V(512 Ref.) 605 495 440
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Refresh Cycles Part NO. C256D V256D VCC 5V 3.3V Refresh cycle 512K Refresh period Normal 8ms L-ver 128ms
RAS UCAS LCAS W
FUNCTIONAL BLOCK DIAGRAM
Control Clocks Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer
VBB Generator
Refresh Timer
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Row Decoder
Performance Range: Speed -5 -6 -7
DQ0 to DQ7
tRAC
50ns 60ns 70ns
tCAC
15ns 15ns 20ns
tRC
90ns 10ns 130ns
tPC
35ns 40ns 45ns
Remark 5V only 5V/3.3V 5V/3.3V
A0 . . A8
Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer Column Decoder Memory Array 262,144 x16 Cells
OE
DQ8 to DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM416C256D, KM416V256D
CMOS DRAM
PIN CONFIGURATION (Top Views)
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KM416C/V256DJ
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KM416C/V256DT
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC
1 U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC
1 U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS
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(SOJ)
(TSOP-II)
Pin Name A0 - A8 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C
Pin Function Address Inputs Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+5V) Power(+3.3V) No Connection
KM416C256D, KM416V256D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN,VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Rating
CMOS DRAM
Units 5V -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 V V E W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70E)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3
*2
3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -1.0
*2
5V Typ 5.0 0 Max 5.5 0 VCC+1.0 *1 0.8
Units V V V V
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Input Leakage Current (Any input 0AVINAVIN+0.3V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VAVOUTAVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0AVINAVIN+0.5V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VAVOUTAVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) Min -5 Max 5 Units uA
3.3V
IO(L) VOH VOL II(L)
-5 2.4 -5
5 0.4 5
uA V V uA
5V
IO(L) VOH VOL
-5 2.4 -
5 0.4
uA V V
KM416C256D, KM416V256D
DC AND OPERATING CHARACTERISTICS (Continued)
Max Symbol Power Speed KM416V254D ICC1 ICC2 ICC3 Don't care Don't care Don't care -5 -6 -7 Don't care -5 -6 -7 -5 -6 -7 Don't care -5 -6 -7 Don't care Don't care 90 80 1 90 80 60 55 0.5 100 90 80 200 100 KM416C254D 110 90 80 2 110 90 80 70 60 55 1 150 110 90 80 300 200
CMOS DRAM
Units mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA
ICC4
Don't care Normal L Don't care L L
ICC5
ICC6 ICC7 ICCS
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V, Din=Don't care, TRC=125us, TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A8=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
KM416C256D, KM416V256D
CAPACITANCE (TA=25E, VCC=5V or 3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A8] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0EA TAA70E, See note 1,2)
Test condition (5V device) : VCC=5.0V3/410%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (3.3V device) : VCC=3.3V3/40.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Symbol Min -5
*1
-6 Min 110 152 Max Min 130 177 60 15 30 0 0 12 50 0 3 50 10K 70 20 70 10K 45 30 20 20 15 5 0 10 0 15 35 0 0 0 0 15 15 15 15
-7 Max
Units ns ns 70 20 35 ns ns ns ns 17 50 ns ns ns 10K ns ns ns 10K 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
Max
tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL
90 132 50 15 25 0 0 3 30 50 15 50 15 20 15 5 0 10 0 10 25 0 0 0 0 10 10 15 13 10K 35 25 10K 12 50
3,4,10 3,4,5 3,10 3 6 2
0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 0 10 10 15 15
4 10
12 12
8 8 7
15
Note)
*1 : 5V
only
KM416C256D, KM416V256D
AC CHARACTERISTICS (Continued)
Parameter Data set-up time Data hold time Refresh period (Normal) Refresh period (L-ver) CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hlod time (CAS -before-RAS refresh) RAS to CAS precharge time CAS precharge time (CBR counter test cycle) Access time from CAS precharge Fast Page mode cycle time Fast Page read-modify-write cycle time CAS precharge time (Fast Page cycle) RAS pulse width (Fast Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Note) *1 : 5V only Symbol Min
*1 -5
CMOS DRAM
-6 Max Min 0 10 8 128 37 72 47 52 10 10 5 20 30 35 77 10 50 30 15 12 0 15 100 90 -50 12 12 0 15 100 110 -50 12 100K 40 82 10 60 35 15 17 0 20 100 130 -50 17 100K 37 82 52 57 10 10 5 20 35 45 97 10 70 40 20 100K 8 128 47 97 62 67 10 10 5 25 40 Max Min 0 15 8 128 -7 Max ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns 11 11 11 6 13 3 7,14 7 7 7 17 18 9,19 9,19 Units Notes
tDS tDH tREF tREF tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tRASS tRPS tCHS
0 10
KM416C256D, KM416V256D
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 50pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDAtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCSAtWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDAtCWD(min), tRWDAtRWD(min), tAWDAtAWD(min) and tCPWDAtCPWD(min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in ealy write cycles and to the W FALLing edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
KM416C/V256D/DL Truth Table
RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L W H H H H H L L L H OE H H L L L H H H H DQ0 - DQ7 Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write -
KM416C256D, KM416V256D
version). 12. tASC, tCAH are referenced to the earlier CAS rising edge.
CMOS DRAM
11. 512cycle of burst refresh must be executed within 8ms before and after self refresh in order to meet refresh specification (L-
13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 14. tCWD is referenced to the later CAS falling edge at word red-modify-write cycle. 15. tCWL is specified from W falling edge to the earlier CAS rising edge. 16. tCSR is referenced to earlier CAS falling low before RAS transition low. 17. tCHR is referenced to the later CAS rising high after RAS transition low.
RAS LCAS
UCAS
tCSR
20. tDS, tDH are specified for earlier CAS falling low.
tCHR
LCAS
UCAS
tDS
DQ0 ~ DQ15 Din
tDH
w

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